Recording apparatus, semiconductor device, and recording head device

ABSTRACT

An apparatus main body controlling section  2  and a memory access controlling section  3  transmit and receive data by means of serial data communication. The memory access controlling section  3  reads various information (the amount of remaining ink, use start year and month, and the like) stored in non-volatile memories  4  and  5  and stores the readout information in a RAM in the memory access controlling section  3.  The apparatus main body controlling section  2  issues an access request command to the RAM to read out and renew the information. When a power supply to a printer is turned off, the apparatus main body controlling section  2  issues an information write back command. The memory access controlling section  3  writes the information in the RAM back to the non-volatile memories  4  and  5.  Reads from and writes to the non-volatile memories  4  and  5  are thus executed via the memory access controlling section  3,  thereby reducing the amount of processing to be executed by the apparatus main body controlling section  2  to access the non-volatile memories  4  and  5.

TECHNICAL FIELD

The present invention relates to a recording apparatus having anon-volatile memory in a recording material accommodating cartridge sothat various data (remaining amount data, use start date data, recordingmaterial type data, manufacturing managing data, etc.) on a cartridgecan be stored in the non-volatile memory to manage use conditions foreach cartridge, and in particular, to a recording apparatus having aninterface circuit (memory access controlling circuit) between a controlsection of a recording apparatus main body and the non-volatile memoryto reduce the amount of processing to be executed by the control sectionto access the non-volatile memory, as well as a semiconductor device foruse as the interface and a recording head apparatus comprising thesemiconductor device for use as the interface.

BACKGROUND ART

Japanese Patent Laid-Open No. 62-184856 (Japanese Patent No. 2594912)describes an ink cartridge and a recording apparatus in which the inkcartridge has a non-volatile memory in which data corresponding to theamount of remaining ink stored in order to manage the amount ofremaining ink for each cartridge.

Japanese Patent Laid-Open No. 8-197748 describes an ink jet printerincluding an ink cartridge having a non-volatile memory in which IDinformation is stored and a printer main body correlating the IDinformation for the ink cartridge read out from the non-volatile memorywith the amount of remaining ink so as to eliminate the need to redetectthe amount of remaining ink when an ink cartridge with the same IDinformation is reinstalled.

The conventional recording apparatus and the like use what is called abit-sequential-access type non-volatile memory that allows data to bewritten thereto and read out therefrom in a bit serial manner, in orderto reduce the number of signal lines between the control section of theprinter main body and the non-volatile memory. Since, however, thenon-volatile memory is accessed in a bit serial manner, a large amountof time is required for writes and readouts. Thus, if the controlsection (a CPU or the like) of the printer main body directly controlsaccess to the non-volatile memory, while the non-volatile memory isbeing accessed, the control section (the CPU or the like) cannot executeother processes. This may causes a delay in a printing process or aresponse to an operational input from an operation section.

The present invention is provided to solve these problems, and it is anobject thereof to provide a recording apparatus having a memory accesscontrolling section between a control section of a recording apparatusmain body and a non-volatile memory to reduce the amount of processingexecuted by the control section to access the non-volatile memory, aswell as a semiconductor device and a recording head apparatus which areused for this purpose.

DISCLOSURE OF THE INVENTION

A recording apparatus according to the present invention ischaracterized by having a memory access controlling section between anapparatus main body controlling section provided in a recordingapparatus main body and a non-volatile memory provided in a recordingmaterial accommodating cartridge, in order to control writes to andreadouts from the non-volatile memory based on commands supplied by theapparatus main body controlling section.

Thus, the recording apparatus according to the present invention isconfigured to execute writes to and readouts from the non-volatilememory via the memory access controlling section, thereby reducing theamount of processing to be executed by the apparatus main bodycontrolling section to access the non-volatile memory.

An embodiment of the recording apparatus according to the presentinvention is characterized in that the memory access controlling sectioncomprises a serial data communicating section for executing serial datacommunication with the apparatus main body controlling section, acommand executing section for interpreting and executing a commandsupplied by the apparatus main body controlling section via the serialdata communicating section, a non-volatile memory write and readoutcontrolling section for executing writes to and readouts from thenon-volatile memory, and a random access memory for temporarily storingdata read out from the non-volatile memory, and in that the apparatusmain body controlling section causes data stored in the non-volatilememory to be transferred to the random access memory, causes variousprocesses to be executed by referencing the data stored in the randomaccess memory to update the data stored in the random access memory, andthen causes the data stored in the random access memory to betransferred to the non-volatile memory.

The serial data communicating section is thus provided to seriallycommunicate data between the apparatus main body controlling section andthe memory access controlling section, thus making it possible to reducethe number of signal lines required between the apparatus main bodycontrolling section and the memory access controlling section.

Further, the random access memory is provided, in which data read outfrom the non-volatile memory are all stored so that the stored data canbe read out in response to a data readout request from the apparatusmain body controlling section, thus making it possible to respond todata readout requests at a high speed.

Furthermore, the apparatus main body controlling section can generate adata write request to renew data in the random access memory and thencause the data renewed in response to the data write request to bewritten to the non-volatile memory. Accordingly, even with a pluralityof data items to be renewed, the plurality of data can be written to thenon-volatile memory with a single write operation.

A semiconductor device according to the present invention ischaracterized by having a memory access controlling section formed on asemiconductor substrate, for controlling writes to and readouts from anon-volatile memory based on commands supplied by an apparatus main bodycontrolling section.

Thus, in the semiconductor device according to the present invention,the memory access controlling section is formed on the semiconductorsubstrate to constitute an integrated circuit, thereby contributing toreducing the size of the recording apparatus.

A recording head apparatus according to the present invention ischaracterized in that a carriage comprising a section for housing arecording material accommodating cartridge including a non-volatilememory has a memory access controlling section for controlling datatransmissions and receptions between a control section of a recordingapparatus main body and a non-volatile memory based on commands suppliedby the control section of the recording apparatus main body.

In the recording head apparatus according to the present invention, thememory access controlling section is thus provided in the carriagecomprising the section for housing the recording material accommodatingcartridge, thereby facilitating the provision of the memory accesscontrolling section.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a block diagram showing the entire configuration of arecording apparatus according to the present invention;

FIG. 2 is a block diagram showing a specific example of a non-volatilememory;

FIG. 3 is a view useful in explaining information stored in thenon-volatile memory;

FIG. 4 is a view useful in explaining an example of information storedin a non-volatile memory provided in a black ink cartridge;

FIG. 5 is a view useful in explaining an example of information storedin a non-volatile memory provided in a color ink cartridge;

FIG. 6 is a block diagram showing a specific example of a memory accesscontrolling section;

FIG. 7 is a view useful in explaining the names of terminals (signalnames) of an integrated circuit for a memory access controlling sectionand their functions;

FIG. 8 is a view useful in explaining various commands supplied by anapparatus main body controlling section;

FIG. 9 is a block diagram of a reception controlling section;

FIG. 10 is a view useful in explaining timings for switching a commandmode designating signal;

FIG. 11 is a view useful in explaining the specifications of avariable-length command and of a response thereto;

FIG. 12 is a view useful in explaining the contents of a group ofcontrol registers and their functions;

FIG. 13 is a view useful in explaining information stored in a RAM;

FIG. 14 is a block diagram of a transmission controlling section;

FIG. 15 is a view useful in explaining a format of serial communicationdata;

FIG. 16 is a perspective view showing the structure of a printingmechanism section of an ink jet printer with a recording apparatusaccording to the present invention applied thereto;

FIG. 17 is a perspective view showing that a carriage is disassembledinto a holder section and a header section;

FIG. 18 is a perspective view of an ink cartridge;

FIG. 19 is a view useful in explaining the structure of a non-volatilememory circuit board;

FIG. 20 is a view (1) useful in explaining how an ink cartridge isinstalled;

FIG. 21 is a view (2) useful in explaining how the ink cartridge isinstalled; and

FIG. 22 is a view useful in explaining how a non-volatile memorysubstrate and a contact forming member of a contact mechanism contactwith each other.

BEST MODE FOR CARRYING OUT THE INVENTION

Embodiments of the present invention will be described below withreference to the accompanying drawings.

FIG. 1 is a block diagram showing the entire configuration of arecording apparatus according to the present invention. A recordingapparatus 1 is composed of an apparatus main body controlling section 2provided in a recording apparatus main body, a memory access controllingsection 3 provided in a carriage comprising an ink cartridge installingsection, a non-volatile memory 4 provided in a black ink cartridge, anon-volatile memory 5 provided in a color ink cartridge, and a recordingcontrolling mechanism (not shown; a mechanism for controlling sheetfeeding, carriage movement, ink ejection, and the like). Thenon-volatile memories 4 and 5 are, for example, EEPROMs that allowelectric writes thereto and electric readouts therefrom. Although FIG. 1shows a configuration comprising the two non-volatile memories 4 and 5,any number of non-volatile memories may be used.

The apparatus main body controlling section 2 controls the entireoperation of the recording apparatus 1 and comprises a microcomputersystem. Various commands and data are transmitted and received betweenthe apparatus main body controlling section 2 and the memory accesscontrolling section 3 by means of serial data communication. Thenon-volatile memories 4 and 5 are of what is called a bit sequentialaccess type that allows data to be written thereto and read outtherefrom in a bit serial manner. The memory access controlling section3 stores data read out from the non-volatile memory 4 or 5 in a RAM inthe memory access controlling section 3.

The apparatus main body controlling section 2 issues a readout commandto the RAM in the memory access controlling section 3 to read outvarious data therefrom. The apparatus main body controlling section 2issues a write command to the RAM in the memory access controllingsection 3 to write various data thereto. The apparatus main bodycontrolling section 2 issues a command for a write to the non-volatilememory, to the memory access controlling section 3 in order to storedata stored in the RAM in the memory access controlling section 3, inthe non-volatile memory 4 or 5.

Thus, the recording apparatus 1 according to the present invention hasthe memory access controlling section 3 between the apparatus main bodycontrolling section 2 and the non-volatile memories 4 and 5 so that thememory accesses controlling section 3 can execute writes to and readoutsfrom the non-volatile memories 4 and 5, thereby making it unnecessaryfor the apparatus main body controlling section 2 to directly access thenon-volatile memories 4 and 5. Accordingly, the amount of processing tobe executed by the apparatus main body controlling section 2 can bereduced. Further the memory access controlling section 3 reads out datastored in the non-volatile memories 4 and 5 and stores them in the RAM.In response to a readout request issued by the apparatus main bodycontrolling section 2, data stored in the RAM are read out for aresponse, thereby enabling a fast response to the readout request.

FIG. 2 is a block diagram showing a specific example of a non-volatilememory. The non-volatile memories 4 and 5 each comprise a memory cell41, a read/write controlling section 42 and an address counter 43. If achip select signal CS is at an L level, the address counter 43 is resetand has a count value of zero. If the chip select signal CS is at an Hlevel, the address counter 43 performs an up-count operation based on aclock signal CK. Accordingly, when the chip select signal CS is changedto the H level, the address 0 is set, and whenever the clock signal CKis supplied, the address can be incremented. If a read/write signal WRis at the L level, the read/write controlling section 42 reads out data(1 bit) stored in the memory cell 41 at an address designated by theaddress counter 43 and outputs the readout data to a data I/O terminalIO. If the read/write signal WR is at the H level, the read/writecontrolling section 42 writes data (1 bit) supplied to the data I/Oterminal IO to the memory cell 41 at the address designated by theaddress counter 43.

FIG. 3 is a view useful in explaining information stored in thenon-volatile memory. The non-volatile memories 4 and 5 in thisembodiment has a storage capacity of 256 bits. The non-volatile memories4 and 5 each store 35 information items. Each information item has avariable bit length. The non-volatile memories 4 and 5 each store dataof a variable length in a bit serial manner. This makes it possible tostore a large amount of information in a limited storage capacity.

Data on the amount of remaining ink, data on the use start years andmonths of ink cartridges, that is, data that must be renewed dependingon the usage of the ink cartridges are stored within the range ofnumbers 1 to 9 (information numbers 0 to 8 and 35 to 43) shown in FIG.3. Thus, when the ink cartridges are actually used, data must be written(renewed) only to the lower addresses in the non-volatile memories 4 and5. Accordingly, when the use of the recording apparatus 1 is ended and apower supply thereto is turned off, data within the range of numbers 1to 9 (information numbers 0 to 8 and 35 to 43) have only to be writtento the non-volatile memories 4 and 5.

The non-volatile memory 4 provided in the black ink cartridge storesdata on the amount of remaining black ink, the use start year and month,and the like. The non-volatile memory 5 provided in the color inkcartridge stores data on the amount of remaining ink, the use start yearand month, and the like for each color ink.

Various data that are not required to be renewed by the user are storedwithin the range of numbers 10 to 35 (information numbers 9 to 34 and 44to 69) shown in FIG. 3. Specifically, these data include data on theversions of the ink cartridges, ink types, the date of manufacture(year, month, and day) of the ink cartridges, the serial numbersthereof, manufacturing sites, recycling of the cartridges, etc.

FIG. 4 is a view useful in explaining an example of information storedin the non-volatile memory provided in the black ink cartridge. In FIG.4, reference numeral 410 denotes a first storage area in which data forrewrite are stored, and reference numeral 420 denotes a second storagearea in which readout only data are stored. The first storage area 410are arranged at addresses that are accessed earlier than the secondstorage area 420 when the non-volatile memory 4 is accessed.

The data for rewrite stored in the first storage area 410 are first andsecond black ink remaining-amount data assigned to storage areas 411 and412, respectively, in terms of an access order. The black ink remainingamount data are assigned to the two storage areas 411 and 412 becausethe data in these areas are alternately rewritten. Thus, the data storedin the storage area 411 are the last rewritten data, the black inkremaining-amount data stored in the storage area 412 precede the lastrewritten data and the data in the storage area 412 is to be writtennext.

The readout only data stored in the second storage area 420 are those onthe opening times (year and month) of the ink cartridges, the versionsof the ink cartridges, ink types such as pigments and dyes, the date ofmanufacture (year, month, and day) thereof, the production linestherefor, the serial numbers thereof, and the presence of recyclingindicating whether the ink cartridge is new or recycled, which data areassigned to storage areas 412 to 430 in terms of an access order.

FIG. 5 is a view useful in explaining an example of information storedin the non-volatile memory provided in the color ink cartridge. In FIG.5, reference numeral 510 denotes a first storage area in which data forrewrite are stored, and reference numeral 550 denotes a second storagearea in which readout only data are stored. The first storage area 510are arranged at addresses that are accessed earlier than the secondstorage area 550 when the non-volatile memory 5 is accessed.

The data for rewrite stored in the first storage area 510 are first andsecond cyan ink remaining-amount data, first and second magenta inkremaining-amount data, first and second yellow ink remaining-amountdata, first and second light cyan ink remaining-amount data, and firstand second light magenta ink remaining-amount data which are assigned tostorage areas 511 to 520, respectively, in terms of an access order. Theink remaining amount data for each color are assigned to the two storageareas because the data in these areas are alternately rewritten as inthe black ink cartridge.

The readout only data stored in the second storage area 550 are those onthe opening times (year and month) of the ink cartridges, the versionsof the ink cartridges, ink types such as pigments and dyes, the date ofmanufacture (year, month, and day) thereof, the production linestherefor, the serial numbers thereof, and the presence of recyclingindicating whether the ink cartridge is new or recycled, which data areassigned to storage areas 551 to 560 in terms of an access order. Sincethese data are the same regardless of the colors, only the data for onecolor are stored as data common to all the colors.

FIG. 6 is a block diagram showing a specific example of the memoryaccess controlling section. The memory access controlling section 3 iscomposed of a serial-data communicating section 11, a receptioncontrolling section 12, a transmission controlling section 13, a commandexecuting section 14, a mode register 15, a group of control registers16, a first RAM 17, a second RAM 18, a non-volatile memory write andread controlling section 19, an output controlling section 20, aneffective-bit length data table 21, a clock generating section 22, anoscillation circuit section 23, a reset circuit section 24, a testingcontrol section 25, and an information and address correlating table 26.

In this embodiment, the memory access controlling section 3 isimplemented as an integrated circuit (semiconductor device) of one chipusing a CMOS gate array. The memory access controlling section 3 maycomprise program control using a one-chip microcomputer having a serialcommunication function built thereinto.

FIG. 7 is a view useful in explaining the names of terminals (signalnames) of the integrated circuit for the access controlling section andtheir functions. Reference RXD denotes an input terminal for a serialdata signal supplied by the apparatus main body controlling section 2.Reference SEL denotes an input terminal for a command mode designatingsignal (command selecting signal) supplied by the apparatus main bodycontrolling section 2. Reference TXD denotes an output terminal for aserial data signal supplied to the apparatus main body controllingsection 2. Reference CS1 denotes an output terminal for a selectionsignal (chip enable signal) for the first non-volatile memory andreference CS2 denotes an output terminal for a selection signal (chipenable signal) for the second non-volatile memory. Reference IO1 denotesan I/O terminal of the first non-volatile memory, and reference IO2denotes an I/O terminal of the second non-volatile memory. Reference RW1denotes an output terminal for a readout/write signal for the firstnon-volatile memory, and reference RW2 denotes an output terminal for areadout/write signal for the second non-volatile memory. Reference CK1is an output terminal for a clock signal for the first non-volatilememory, and reference CK2 is an output terminal for a clock signal forthe second non-volatile memory. Reference PW1 denotes a power supplyterminal for the first non-volatile memory, and reference PW2 denotes apower supply terminal for the second non-volatile memory. ReferencesOSC1 and OSC2 denote connection terminals for a ceramic oscillator, acrystal vibrator, and the like. Reference RST denotes an input terminalsfor an initial reset signal. Reference ES denotes an input terminal forselecting a write time for the non-volatile memory. References M1 to M4denote input terminals for a testing signal for selecting a monitoroutput. Reference VCC1 denotes a +5-V power supply terminal, referenceVCC2 denotes a +3.3-V power supply terminal, and reference VSS denotes aground (GND) terminal.

The symbols shown in the I/O column in FIG. 7 have the followingmeanings: Reference IN denotes an input, reference OUT denotes anoutput, and reference Tri denotes a tristate-side output. Theinitial-value column indicates logical levels obtained when this memoryaccess controlling section integrated circuit is initially reset.Further, the items enclosed by the parentheses in the initial-valuecolumn indicate the level of each output terminal obtained immediatelyafter the outputs to the non-volatile memory have been activatedfollowing the setting of an access permission in a non-volatile memoryaccess permission setting register, described later. Reference H denotesa high level, reference L denotes a low level, and reference HiZ denotesa high impedance state.

Three signal lines connect the memory access controlling section 3 tothe apparatus main body controlling section 2 (see FIG. 1) as shown inFIG. 6. Reference RXD denotes received data (data transmitted from theapparatus main body controlling section 2), reference TXD denotestransmitted data (data received by the apparatus main body controllingsection 2), and reference SEL denotes a command mode designating signalwhether a command transmitted by the apparatus main body controllingsection 2 has a fixed or a variable length. The L level of the commandmode designating signal SEL indicates an 8-bit fixed length command,whereas its H level indicates a variable-length command.

The serial data communicating method comprises a UART (UniversalAsynchronous Receiver Transmitter) method. The data length is 8 bits,the start bit length is 1 bit, the stop bit length is 1 bit, and noparity bit is used. Data are transferred from an LSB (Least SignificantBit) to an MSB (Most Significant Bit). The baud rate is 125 kbps.

A reception section 11 a in the serial-data communicating section 11monitors the logical level of the received data RXD with a0.5-microsecond cycle based on the clock TCLK of 2 MHz frequencysupplied by the clock generating section 22. Thus, one-bit data undergo16 level detections. Upon recognizing the start bit based on the factthat the logical level of the received data RXD changes from H level toL level, the reception section 11 a repeats sampling the logical levelof the received data RXD with a 16-clock cycle starting from the eighthclock TCLK from the point at which the start bit has been recognized.This allows the logical level of the received data RXD to be sampledsubstantially at the middle of each bit.

After the start bit has been recognized, if the logical level of thereceived data RXD returns to H at the next clock, the reception section11 a considers the previously detected L level as noise to restart anoperation of detecting the start bit. Further, if the logical level ofthe start bit sampled at the eighth clock TCLK from the point at whichthe start bit has been recognized is not L, the reception section 11 aaborts subsequent data sampling and resumes the start bit detectingoperation. Furthermore, if the sampling level of the stop bit is not H,the reception section 11 a invalidates all the sampled data. Thisprevents reception of abnormal data resulting from different baud ratesbetween the transmitting side and the receiving side or from otherfactors. Upon normally receiving all of the start bit, 8-bit data, andstop bit, the reception section 11 a converts the received serial 8-bitdata into parallel data and outputs them to the reception controllingsection 12 as parallel received data RD.

A transmission section 11 b in the serial data communicating section 11converts parallel transmitted data TD supplied by the transmissioncontrolling section 13, into serial data, adds the start bit and thestop bit to the serial data to generate the transmitted data TXD, andtransmits the generated transmitted data TXD at a predetermined baudrate.

FIG. 8 is a view useful in explaining various commands supplied by theapparatus main body controlling section. FIG. 8(a) shows an 8-bit fixedlength command supplied by the apparatus main body controlling sectionwhen the command mode designating signal SEL has the L level. There arethree types of 8-bit fixed length commands: a power-off process command,an initialization command, and a mode setting command. The power-offprocess command requests in power-off the recording apparatus 1 thatvarious data stored in the RAM 17 or 18 are written to the non-volatilememory 4 or 5 and that after the write has been completed, all outputsto the non-volatile memories 4 and 5 are initialized to their resetstates established immediately after power-on. The initializationcommand requests that all the circuits in the memory access controllingsection 3 are initialized to its reset state established immediatelyafter power-on. The mode setting command sets an operation mode usedwhen the command mode designating signal SEL has become the H level. Themode setting command designates the operation mode with the 4 leastsignificant bits. For example, if the 4 least significant bits are 0010,an operation mode 2 has been set.

The apparatus main body controlling section 2 is adapted to use 4-bitmode information to manage a plurality of operation modes ranging frommodes 0 to 15. For example, the entire operation of the recordingapparatus are commonly controlled in the mode 0, and print data arecontrolled in the mode 1. In the mode 2, the non-volatile memories 4 and5 can each be accessed via the memory access controlling section. In themode 3, a head sensor system is controlled. Even if data transmittedfrom the apparatus main body controlling section 2 are supplied to aplurality of control sections (for example, an ink ejection controllingsection, a carriage movement controlling section, and a sheet feedcontrolling section), designation of an operation mode allows only thecontrol section compatible with this operation mode to operate based onthe data transmitted from the apparatus main body controlling section 2.

In this embodiment, the memory access controlling section 3 is adaptedto access the two non-volatile memories 4 and 5. Thus, if a plurality ofmemory access controlling sections 3 are provided and assigned withdifferent operation modes, a large number of non-volatile memories canbe accessed.

Even if, for example, independent cartridges are provided for inks suchas cyan, light cyan, magenta, light magenta, yellow, and black and eachcomprise a non-volatile memory, then, for example, six non-volatilememories can be accessed by using, for example, three memory accesscontrolling sections 3. Thus, it will be easy to expand the constructionof the recording apparatus by using the operation mode.

FIG. 8(b) shows a variable-length command supplied by the apparatus mainbody controlling section when the command mode designating signal SELhas the H level. The variable-length command comprises a plurality ofbytes. In the first byte, the 4 most significant bits designate theoperation mode and the 4 least significant bits designate the bytelength of this command. The operation mode 2 (0010) is essentially setfor commands to the memory access controlling section 3. The byte lengthin the 4 least significant bits contains data representative of the bytelengths of the second subsequent bytes (data representative of the bytelengths of the succeeding bytes exclusive of the first byte).

In the second byte, the 4 most significant bits designate a command, andthe 4 least significant bits designate a data length. If the 4 mostsignificant bits of the second byte is 0000, this represents a commandfor a data readout; if it is 1000, this represents a command for a datawrite. The 4 least significant bits of the second byte contain dataindicating the byte length of write data supplied after address data ifthe command requires a data write, or contain data indicating the bytelength of readout data if the command requires a data readout. In thisembodiment, up to 4 bytes of data can be supplied with a single writerequest command.

The third and fourth bytes contain data indicating addresses to or fromwhich data are to be written or read out. The figure shows that thethird byte indicates the 8 least significant bits for the addresses,while the fourth byte indicates the 8 most significant bits for theaddresses. This makes it possible to designate a wide address range withup to 16 bits. With regards to this, in this embodiment, the addressrange to and from which data are to be written or read out can bedesignated with an 8-bit address, so that only the 8 least significantbits of the address data are used. The designated address is an addressin the RAMs and control registers (it is not an address in thenon-volatile memories)

The fifth and subsequent bytes contain write data. The data contained inthe fifth byte are written to the address indicated by the address data,and the data contained in the sixth and subsequent bytes are written tocorresponding incremented addresses starting with the one larger thanthe address indicated by the address data, by one.

FIG. 9 is a block diagram of the reception controlling section. Thereception controlling section 12 comprises data latch circuits 12 a to12 h for latching the parallel 8-bit received data RD supplied by theserial data communicating section 11, and a transfer controlling section12 i for controlling the write of the received data RD to the data latchcircuits 12 a to 12 h and the transfer thereof to the command executingsection 14 based on the command mode designating signal SEL and thereceived data RD.

If the command mode designating signal SEL is at the L level (it is foran 8-bit fixed length command), the transfer controlling section 12 isupplies the received data RD supplied by the serial-data communicatingsection 11 to the command executing section 14.

If the command mode designating signal SEL is at the H level (it is fora variable-length command), the transfer controlling section 12 i storesthe received data RD transferred from the serial-data communicatingsection 11, in the first data latch circuit 12 a. The transfercontrolling section 12 i then recognizes the command length of thevariable-length command based on the 4 least significant bits of thedata stored in the first data latch circuit 12 a. The transfercontrolling section 12 i sequentially stores the received datasequentially supplied by the serial-data communicating section 11, inthe second to eighth data latch circuits 12 a to 12 h. Upon detectingthat an amount of received data corresponding to the bytes indicated bythe command length have been stored in the data latch circuits, thetransfer controlling circuit 12 i transfers the series of data stored inthe data latch circuits to the command executing section 14 and theninitializes each of the data latch circuits to allow for the storage ofthe next variable-length command.

The transfer controlling section 12 i waits for the next received datato be supplied until data of the number of bytes indicated by thecommand length are received. If the command mode designating signal SELbecomes the L level before data of the number of bytes indicated by thecommand length are received, the transfer controlling section 12 iinitializes all the data stored in the data latch circuits to allow forthe reception of the next command. Thus, even while transmitting thevariable-length command, the apparatus main body controlling section 2can cancel the variable-length command being transmitted, by changingthe command mode designating signal SEL to the L level.

FIG. 10 is a view useful in explaining timings for switching the commandmode designating signal. FIG. 10(a) shows the received data RXD and FIG.10(b) shows the command mode designating signal SEL. The apparatus mainbody controlling section 2 switches the logical level of the commandmode designating signal SEL between the stop bit and the next start bit.

The transfer controlling section 12 i shown in FIG. 9 gives top priorityto the designation with the command length if the number of bytesindicated by the command length is unequal to that indicated by the datalength. If, for example, the command length indicates a series of 5-bytedata, while the data length indicates 4 bytes as the number of databytes, the transfer controlling section 12 i determines that all of theseries of variable-length commands have been received when 2 bytes ofdata have been stored in each of the fifth and sixth data latch circuits12 e and 12 f. The transfer controlling section 12 i then transfers thedata stored in the data latch circuits to the command executing section14 to allow for the storage of the next command.

If a mode register, described later, is set to the operation mode 2, thetransfer controlling section 12 i gives top priority to the designationfor the operation mode 2 set in the mode register and accepts anycommand as one for the operation mode 2 (in other words, as a command tothe memory access controlling section) even if the operation mode (thedesignation with the 4 most significant bits of the received data storedin the first data latch circuit 12 a) supplied via the serial-datacommunicating section 11 indicates an operation mode other than theoperation mode 2.

In this embodiment, three types of data lengths including 1 byte, 2bytes, and 4 bytes can be set and the data length can be set with 4-bitdata. Thus, if data indicating a data length other than these threetypes, the data length is determined to be designated as 4 bytes.Specifically, if data indicating a data length of 3 bytes or 5 to 15bytes, the transfer controlling section 12 i determines that the datalength is 4 bytes.

Further, in this embodiment, each address in the RAMs 17 and 18 and thecontrol register 16 can be designated with 8 bits. Thus, the address canbe designated only with the lowest address stored in the third datalatch circuit 12 c. Thus, the data on the highest address stored in thefourth data latch circuit 12 d are not required to be transferred to thecommand executing section 14. Moreover, the fourth data latch circuit 12d is not required to be provided. In this case, the transfer controllingsection 12 i discards the received data on the highest address suppliedby the serial-data communicating section 11 and stores data suppliednext to the highest address in the fifth data latch circuit 12 e.

When supplied with a command received from the reception controllingsection 12, the command executing section 14 shown in FIG. 6 interpretsand executes that command. When supplied with the mode set command, thecommand executing section 14 writes data for the operation modeindicated by the mode set command, to the mode register 15. In thiscase, the 4-bit data 0010 indicative of a memory access controllingoperation mode are written to the mode register 15. The operation modeMD set in the mode register 15 is supplied to the reception controllingsection 12.

When supplied with the initialization command, the command executingsection 14 supplies a reset signal generation request to the resetcircuit section 24 to generate a reset signal RS. This initializes(resets) each of the circuit sections of the memory access controllingsection 3.

If the variable-length command is transferred from the receptioncontrolling section 12, the command executing section 14 interprets thecontents of the variable-length command and executes a process such as awrite to or a readout from the group of control registers 16, the firstRAM 17, or the second RAM 18.

FIG. 11 is a view useful in explaining the specifications of thevariable-length command and of a response thereto. This figure shows thespecification of the variable-length command (request) in a section (a).The variable-length command includes a readout command (READ) and awrite command (WRITE) The mode is set at the 4-bit value (0010),indicating the operation mode 2.

The command length indicates the byte length of the command with 4 bits.The 4-bit command value 0000 indicates the readout command, whereas the4-bit command value 1000 indicates the write command. The data lengthdesignates the number of bytes of data for readout and write. The datalength can be set to 1 byte, 2 bytes, and 4 bytes. Zero byte, 3 bytes,and 5 to 15 bytes are prohibited from being set. The address comprises16 bits and is designated as 8 least significant bits and 8 mostsignificant bits as shown in FIG. 8. This embodiment uses only the 8least significant bits. For the write command (WRITE), data to bewritten are set to comprise sets of 8 bits (bytes).

The section (b) in FIG. 11 indicates the specification of a response tothe read command. The mode is set to the 4-bit value (0010), designatingthe operation mode 2. The data length designates the number of bytes ofdata as a response based on the read command. The data length can be setto 1 byte, 2 bytes, and 4 bytes. Zero byte, 3 bytes, and 5 to 15 bytesare prohibited from being set. Data to be provided as a response are setto comprise sets of 8 bits (bytes).

FIG. 12 is a view useful in explaining the contents of the group ofcontrol registers and their functions. The group of control registers 16comprises a plurality of registers. The group of control registers 16are assigned with addresses 80 to 92 in the hexadecimal notation.

The address 80 (hexadecimal notation) corresponds to a non-volatilememory access permission setting register in which 2-bit data are set.Each non-volatile memory (each cartridge) is assigned with one bit. Theleast significant bit is set to indicate whether an access to the firstnon-volatile memory is permitted, and the most significant bit is set toindicate whether an access to the second non-volatile memory ispermitted.

The bit value of 0 prohibits the access to the non-volatile memory. Inthis case, the terminals are set by the output controlling section 20 asfollows: The power supply terminals PW1 and PW2 are in an off statewhere no power is supplied to the non-volatile memories, and the chipselect signal output terminals CS1 and CS2, the clock supply terminalsCK1 and CK2, the read/write signal output terminals RW1 and RW2, and thedata I/O terminals IO1 and IO2 are all in a high impedance state.

The bit value of 1 causes the output controlling section 20 to set thepower supply terminals PW1 and PW2 in an on state where power issupplied to the non-volatile memories. The chip select signal outputterminals CS1 and CS2, the clock supply terminals CK1 and CK2, theread/write signal output terminals RW1 and RW2, and the data I/Oterminals IO1 and IO2 are all set in a controllable (active) state bythe non-volatile memory write and read controlling section 19.

The address 84 (hexadecimal notation) corresponds to a non-volatilememory readout permission setting register in which 2-bit data are set.Each non-volatile memory (each cartridge) is assigned with one bit. Theleast significant bit is set to indicate whether a readout from thefirst non-volatile memory is permitted, and the most significant bit isset to indicate whether a readout from the second non-volatile memory ispermitted. The bit value of 0 prohibits the readout, whereas the bitvalue of 1 permits the readout.

The address 85 (hexadecimal notation) corresponds to a non-volatilememory all-area readout setting register. When arbitrary data arewritten to the non-volatile memory all-area readout setting register(the apparatus main body controlling section 2 issues a write commandindicating an address in the non-volatile memory all-area readoutsetting register), all the data stored in the non-volatile memories canbe read out via the non-volatile memory write and readout controllingsection 19. However, the access to the non-volatile memories must bepermitted beforehand and the permission for the readout must be setbeforehand.

The address 86 (hexadecimal notation) corresponds to an area storing anall-area readout busy flag indicating that data are being read out fromall the areas. The non-volatile memory write and readout controllingsection 19 sets the all-area readout busy flag to one before an all-areareadout operation is started, and sets this flag to zero when theall-area readout operation is completed.

The address 88 (hexadecimal notation) corresponds to a non-volatilememory all-area write permission setting register in which 2-bit dataare set. Each non-volatile memory (each cartridge) is assigned with onebit. The least significant bit is set to indicate whether an all-areawrite to the first non-volatile memory is permitted, and the mostsignificant bit is set to indicate whether an all-area write to thesecond non-volatile memory is permitted. The bit value of 0 prohibitsthe write, whereas the bit value of 1 permits the write.

The address 89 (hexadecimal notation) corresponds to a non-volatilememory all-area write setting register. When arbitrary data are writtento the non-volatile memory all-area write setting register (a writeoperation is performed on the non-volatile memory all-area write settingregister), data can be written to all the areas of the non-volatilememories via the non-volatile memory write and readout controllingsection 19. However, the access to the non-volatile memories must bepermitted beforehand and the permission for the all-area write must beset beforehand.

The address 8A (hexadecimal notation) corresponds to an area storing anall-area write busy flag indicating that data are being written to allthe areas. The non-volatile memory write and readout controlling section19 sets the all-area write busy flag to one before an all-area writeoperation is started, and sets this flag to zero when the all-area writeoperation is completed.

The address 8C (hexadecimal notation) corresponds to a non-volatilememory limited write permission setting register in which 2-bit data areset. Each non-volatile memory (each cartridge) is assigned with one bit.The least significant bit is set to indicate whether a limited write tothe first non-volatile memory is permitted, and the most significant bitis set to indicate whether a limited write to the second non-volatilememory is permitted. The bit value of 0 prohibits the limited write,whereas the bit value of 1 permits the limited write.

The address 8D (hexadecimal notation) corresponds to a non-volatilememory limited write setting register. When arbitrary data are writtento the non-volatile memory limited write setting register (a writeoperation is performed on the non-volatile memory limited write settingregister), data can be written to limited areas of the non-volatilememories via the non-volatile memory write and readout controllingsection 19. However, the access to the non-volatile memories must bepermitted beforehand and the permission for the limited write must beset beforehand.

The address 8E (hexadecimal notation) corresponds to an area storing alimited write busy flag indicating that a limited write is beingexecuted. The non-volatile memory write and readout controlling section19 sets the limited write busy flag to one before a limited writeoperation is started, and sets this flag to zero when the limited writeoperation is completed.

The address 90 (hexadecimal notation) corresponds to a power-off writepermission setting register in which 2-bit data are set. Eachnon-volatile memory (each cartridge) is assigned with one bit. The leastsignificant bit is set to indicate whether a power-off write to thefirst non-volatile memory is permitted, and the most significant bit isset to indicate whether a power-off write to the second non-volatilememory is permitted. The bit value of 0 prohibits the power-off write,whereas the bit value of 1 permits the power-off write.

The address 92 (hexadecimal notation) corresponds to an area storing apower-off write busy flag indicating that a power-off write is beingexecuted. The non-volatile memory write and readout controlling section19 sets the power-off write busy flag to one before a power-off writeoperation is started, and sets this flag to zero when the power-offwrite operation is completed. Further, the non-volatile memory write andreadout controlling section 19 sets the contents of the non-volatilememory access permission setting register to initial values (all bits tozero) when the power-off write operation is completed.

The power-off write is executed based on the power-off process commandshown in FIG. 8(a). In the power-off write, data are written to over alimited address range from the leading address in the non-volatilememory to a preset predetermined address.

As described previously, data such as the amount of remaining ink, forexample, which must be renewed depending on the usage of the recordingapparatus are stored within the address range from the leading addressin the non-volatile memory to the preset predetermined address. Further,data such as manufacturing conditions for the ink cartridges which arenot required to be renewed by the user are stored after thepredetermined address. Accordingly, if the recording apparatus is usedby the user, data are renewed over the limited address range of thenon-volatile memory.

FIG. 13 is a view useful in explaining information stored in the RAM.The RAMs 17 and 18 are configured to contain 8 bits×40 words. In thisembodiment, the first RAM 17 is assigned with addresses 00 to 27 in thehexadecimal notation, while the second RAM 18 is assigned with addresses40 to 67 in the hexadecimal notation.

The first RAM 17 is provided so as to correspond to the firstnon-volatile memory 4 provided in the black ink cartridge. Variousinformation (information 0 to 34) stored in the first non-volatilememory 4 is read out via the non-volatile memory write and readoutcontrolling section 19 and stored in the first RAM 17.

The second RAM 18 is provided so as to correspond to the secondnon-volatile memory 5 provided in the color ink cartridge. Variousinformation (information 35 to 69) stored in the second non-volatilememory 5 is read out via the non-volatile memory write and readoutcontrolling section 19 and stored in the second RAM 18.

There is registered beforehand in the effective-bit-length data table 21shown in FIG. 6, the relationship between the information numbers of theinformation stored in the non-volatile memories and the number of databits in the information. The effective-bit-length data table 21 also hascorrelation data between addresses in each of the group of controlregisters 16 and corresponding effective bit lengths registered thereinbeforehand. There are also registered beforehand in theeffective-bit-length data table 21, correlation data between addressesin the RAMs 17 and 18 and effective bit lengths for data stored at theseaddresses.

There is registered in the information and address correlating table 26,the correlationship between information numbers and addresses in the RAMwhere the information is stored.

The non-volatile memory write and readout controlling section 19identifies, for each information number, the data of a variable lengthand in bits which have been read out from the non-volatile memories 4and 5, by referencing the effective-bit-length data table 21. Then, ifthe data corresponding to each information number have less than 8 bits,the non-volatile memory write and readout controlling section 19 addszeros to the most significant bit to obtain 8-bit data. Further, if thedata corresponding to each information number contain 9 bits or more,the non-volatile memory write and readout controlling section 19separates the data into the 8 least significant bits and the remainingdata, and if the remaining data contain less than 8 bits, thenon-volatile memory write and readout controlling section 19 adds zerosto the most significant bit to obtain 8-bit data. The non-volatilememory write and readout controlling section 19 then references theinformation and address correlating table to write the information eachcomposed of 8 bits to predetermined addresses in the RAMs 17 and 18.

To write the information stored in the RAMs 17 and 18 back to thenon-volatile memories 4 and 5, the non-volatile memory write and readoutcontrolling section 19 performs the readout operation in the reverseorder to generate sequential data in bits and of a variable length.

The output controlling section 20 comprises tristate buffer circuits fordriving the output terminals PW, CS, RW, and CK, a bidirectional buffercircuit connected to the IO terminal, circuits for controlling theoutput state of the tristate buffers, output signal switching circuitsfor switching an input signal to each buffer circuit between an accessstate where the non-volatile memories 4 and 5 can be accessed and a testmode, described later, and other circuits (none of these circuits areshown).

The tristate buffer circuit for driving the power supply terminals PW1and PW2 has a high current driving capability. When the accesspermission setting register of the group of control registers 16 is setto the state where the access to the non-volatile memories is permitted,the tristate buffer circuit with a high current driving capability hasits output driven to the H level to cause the power supply terminals PW1and PW2 to supply power to the non-volatile memories 4 and 5.

The non-volatile memory write and readout controlling section 19 drivesthe terminals CS, RW, CK, and IO via the output controlling section 20to access the non-volatile memories 4 and 5. To read information outfrom the non-volatile memory 4 or 5, the non-volatile memory write andreadout controlling section 19 changes the chip select terminal CS fromL level to H level to make the non-volatile memory 4 or 5 operative, andsets the read/write signal output terminal RW to the L level to set thenon-volatile memory 4 or 5 in the readout mode. After the period of timerequired to establish a data output from the non-volatile memory 4 or 5has passed, the non-volatile memory write and readout controllingsection 19 loads the logical level of the data I/O terminal IO to readdata out from the leading address in the non-volatile memory 4 or 5,supplies a clock for incrementing the address in the non-volatilememory, to the clock supply terminal CK to increment the address in thenon-volatile memory, and then reads data out from the next address. Thisoperation is repeated until the final address in the non-volatilememory, to read out all the data stored in the non-volatile memory.

To write information to the non-volatile memory, the non-volatile memorywrite and readout controlling section 19 changes the chip selectterminal CS from L level to H level to make the non-volatile memory 4 or5 operative, and sets the read/write signal output terminal RW to the Hlevel to set the non-volatile memory 4 or 5 in the write mode. Then,while allowing write data (H or L level) to be output to the data I/Oterminal IO, the non-volatile memory write and readout controllingsection 19 changes the clock terminal CK from L level to H level. Whenthe clock signal changes from L level to H level, the non-volatilememory 4 or 5 loads and stores the data at the leading address in amemory cell. Then, the non-volatile memory write and readout controllingsection 19 changes the clock terminal CK from H level to L level toincrement the address in the non-volatile memory 4 or 5. Thenon-volatile memory write and readout controlling section 19 then allowsthe outputting of data to be stored at the next address and changes theclock terminal CK from L level to H level to write the data to the nextaddress. This operation is repeated until a predetermined address.

The non-volatile memory write and readout controlling section 19comprises a circuit section for executing writes to and readouts fromthe first non-volatile memory and a circuit section for executing writesto and readouts from the second non-volatile memory, in order tosimultaneously read out or write back information from or to the twonon-volatile memories. This enables writes to and readouts from thenon-volatile memories 4 and 5 to be performed in a short time.

When supplied with the variable-length command by the receptioncontrolling section 12, the command executing section 14 determineswhether the command is for a write or for a readout based on the command(4 most significant bits of the second byte) shown in FIG. 8(b). In thiscase, if the command composed of 4 bits have the data 0000, it is for areadout; if the command composed of 4 bits have the data 1000, it is fora write. If the command has data other than 0000 or 1000, the commandexecuting section 14 discards the series of variable-length commands andwaits for the next command to be transferred.

When supplied with the write request command, the command executingsection 14 writes the first data (data indicated by the fifth byte ofthe variable-length command) to the address indicated by the lowestaddress. When supplied with the second data, the command executingsection write the second data (data indicated by the sixth byte of thevariable-length command) to the address larger than the one indicated bythe lowest address, by one. When supplied with the third and fourthdata, the command executing section write the third and fourth data(data indicated by the seventh and eighth bytes of the variable-lengthcommand) to the addresses larger than the one indicated by.the lowestaddress, by two and three, respectively.

In writing the data to the indicated address, the command executingsection 14 references the effective-bit-length data table 21 toascertain the effective bit length for the data to be stored at thataddress. If any bit beyond the effective bit length for the datasupplied by the apparatus main body controlling section 2 has a value of1, the command executing section 14 changes the value of this bit tozero before writing the changed data to the corresponding register. Whensupplied with a command for a write of the 8-bit data 11111111 to theaccess permission setting register corresponding to the address 80(hexadecimal notation), the command executing section 14 ascertains thatthe effective bit length for the access permission setting register is 2bits based on the effective-bit-length data table 21, changes the valuesof bits beyond the effective bit length to zero to generate data00000011, and writes the generated data 00000011 to the accesspermission setting register corresponding to the address 80 (hexadecimalnotation).

When supplied with the readout request command, the command executingsection 14 recognizes the number of bytes of the readout request basedon the data length (4 least significant bits of the second byte) shownin FIG. 8(b) If the readout request is for one byte, then based on theaddress indicated by the lowest address, the command executing section14 reads out the data stored at this address. If the readout request isfor two bytes, then the command executing section 14 reads data out fromthe address indicated by the lowest address and from the next address(the indicated address+1). If the readout request is for four bytes,then the command executing section 14 reads data out from the addressindicated by the lowest address and from the addresses equaling theindicated one+1, the indicated one+2, and the indicated one+3.

The command executing section 14 supplies data on the byte length of thereadout data to the transmission controlling section 13 and thensupplies the actually readout data thereto.

FIG. 14 is a block diagram of the transmission controlling section. Thetransmission controlling section 13 comprises five data latch circuits13 a to 13 e and a transfer controlling section 13 f. The transfercontrolling section 13 f causes the first data latch circuit 13 a tostore the operation mode (0010) in the 4 most significant bits and thedata length (the byte length of the readout data) in the 4 leastsignificant bits. The transfer controlling section 13 f causes thesecond to fifth data latch circuits 13 b to 13 f to store the first tofourth readout data supplied by the command executing section 14. Uponascertaining, based on the data on the data length, that a predeterminednumber of data have been obtained, the transfer controlling section 13 fsequentially transfers the data stored in the data latch circuits 13 ato 13 e to the serial-data communicating section 11.

The transmission section 11 b in the serial-data communicating section11 shown in FIG. 6 converts the parallel transmitted data TDsequentially transferred from the transmission controlling section 13into serial data and sequentially sends the resulting data to theapparatus main body controlling section 2, as described previously.

FIG. 15 is a view useful in explaining a format of serial communicationdata. FIG. 15(a) shows a format used to transmit data less than 8 bits.If 5-bit information is stored in the non-volatile memory as shown inFIG. 15(i), the data to be serially transmitted have zeros inserted intothe 3 most significant bit positions as shown in FIG. 15(ii) and aretransmitted as 1-byte (8-bit) data. In this manner, the data less than 1byte are arranged at the least significant bit positions, with zerosplaced in the most significant bit positions.

FIG. 15(b) shows a format used to transmits data more than 8 bits. If10-bit information is stored in the non-volatile memory as shown in FIG.15(iii), the 10-bit data are divided into 2-byte data sets fortransmission as shown in FIG. 15(iv). Specifically, the 8leastsignificant bits of the 10-bit data are first transmitted as the firstbyte. Then, the 2 most significant bits of the 10-bit data are arrangedat the least significant bit positions and zeros are inserted into themost significant bit positions as dummy data to thereby convert the10-bit data into 8-bit (1-byte) data, which are then transmitted as thesecond byte.

The reset circuit section 24 shown in FIG. 6 generates a reset signal RSif the logical level of the power-on reset signal RST is L. The circuitsections in the memory access controlling section 3 are initialized(reset) based on the reset signal RS. Further, when supplied with areset signal generating signal by the command executing section 14, thereset circuit section 24 generates the reset signal RS. Thus, theapparatus main body controlling section 2 transmits the initializationcommand shown in FIG. 8(a) to initialize each of the circuit sections inthe memory access controlling section 3.

The oscillating circuit section 23 comprises a crystal vibrator, aceramic oscillator X, or the like to generate a raw clock signal of, forexample, 16 MHz frequency. The clock generating section 22 divides theraw clock signal to obtain the clock signal TCLK of, for example, 2-MHzfrequency. Further, the clock generating section 22 generates the clocksignals CK1 and CK2 for the non-volatile memories 4 and 5. The clocksignals CK1 and CK2 for the non-volatile memories 4 and 5 can have theirfrequencies switched between two levels depending on the logical levelof a clock cycle selecting signal ES. This accommodates non-volatilememories with different write times.

The output controlling section 20 controls the states of the signal I/Oterminals of the non-volatile memories 4 and 5 as described previously.The testing control section 25 tests the memory access controllingsection 3 for operation. Normal operational conditions are establishedwhen 4-bit testing signals M1 to M4 are set to the L level. If otherconditions are set, a test mode is entered, thereby making it possibleto output the operational conditions of the internal circuit includingthe data in the registers and RAMs, to the terminals PW, CS, RW, IO, andCK and other terminals via the output controlling section 20. Thisfacilitates checking of the operational conditions of the internalcircuit.

Next, the operation of the above configuration will be explained. Theapparatus main body controlling section 2 sets the command modedesignating signal SEL to the L level and then transmits theinitialization command. In receipt of the initialization command, thememory access controlling section 3 initializes the entire circuit tothe same state as that established upon power-on. Then, the apparatusmain body controlling section 2 transmits the mode setting command tocause the mode register 15 in the memory access controlling section 3 toset the operation mode 2. Thereafter, the apparatus main bodycontrolling section 2 sets the command mode designating signal SEL tothe H level.

After the operation mode 2 is set in the mode register 15 to set thecommand mode designating signal SEL to the H level, even if theoperation mode in a command supplied by the apparatus main bodycontrolling section 2 is not 2, the memory access controlling section 3can accept that command as one for the operation mode 2.

The apparatus main body controlling section 2 sequentially issues writecommands to set a value for each of the group of control registers 16 sothat the memory access controlling section 3 can access the non-volatilememories 4 and 5. Then, the apparatus main body controlling section 2issues a write command indicating addresses in the all-area readoutcontrolling register. Thus, the non-volatile memory write and readoutcontrolling section 19 reads the information stored in the non-volatilememories 4 and 5 and stores the readout information in the RAMs 17 and18.

The information stored in the non-volatile memories 4 and 5 hasdifferent bit lengths for different pieces of information. Thenon-volatile memory write and readout controlling section 19 partitionsthe information by referencing the effective-bit-length data table 21 inwhich the contents shown in FIG. 3 are registered. The non-volatilememory write and readout controlling section 19 modifies data less than8 bits to 8-bit data by adding zeros to the missing bits, and modifiesdata more than 8 bits to 2-byte data. The non-volatile memory write andreadout controlling section 19 then stores the data composed of sets of8 bits, at predetermined addresses in the RAMs 17 and 18 by referencingthe information and address correlating table 26 in which the contentsshown in FIG. 13 are registered. Thus, all the information stored in thefirst non-volatile memory 4 is stored in the first RAM 17, while all theinformation stored in the second non-volatile memory 5 is stored in thesecond RAM 18.

The apparatus main body controlling section 2 can obtain variousinformation such as data on the amount of remaining ink, the use startyear and month of the cartridges, and ink types, for example, bydesignating addresses in the RAMs 17 and 18 and issuing a readoutrequest. The apparatus main body controlling section 2 can alsoascertain the current set conditions by reading the contents out fromthe group of control registers 16.

The apparatus main body controlling section 2 manages the amount of inkwhich has been used in connection with the execution of printoperations. The apparatus main body controlling section 2 issues arequest for a write of data on the renewed amount of ink to renew thedata in the RAMs 17 and 18 relating to the amount of remaining ink.

Before turning off the power supply to the recording apparatus, theapparatus main body controlling section 2 sets the command modedesignating signal SEL to the L level and then transmits the power-offcommand. When supplied with the power-off command, the memory accesscontrolling section 3 writes the data stored in the RAMs 17 and 18 backto the non-volatile memories 4 and 5. This causes the renewed data onthe amount of remaining ink to be stored in the non-volatile memories 4and 5. This write back to the non-volatile memories 4 and 5 based on thepower-off command is directed only at information (numbers 1 to 9 shownin FIG. 3, specifically, data such as the amount of remaining ink whichmust be renewed by the user) set at lower addresses in the non-volatilememories 4 and 5. Accordingly, the write back to the non-volatilememories 4 and 5 can be completed in a short time, and no other data arerewritten.

The write back to the non-volatile memories 4 and 5 can also be executedby issuing from the apparatus main body controlling section 2 a commandfor a write of a command for permitting a limited write to a limitedwrite permitting register shown in FIG. 12.

FIG. 16 is a perspective view showing the structure of a printingmechanism section of an ink jet printer with a recording apparatusaccording to the present invention applied thereto. The printingmechanism section 100 of the ink jet printer apparatus shown in FIG. 16comprises a carriage 103 connected to a drive motor 102 via a timingbelt 101 so as to reciprocate in a sheet width direction of recordingpaper P. The carriage 103 has a holder 104 formed therein and comprisingblack ink cartridge storage section 104 a and a color ink cartridgestorage section 104 b, and has a recording head 105 on the underside ofthe carriage 103.

FIG. 17 is a perspective view showing that the carriage is disassembledinto a holder section and a header section. Ink supply needles 106 and107 in communication with the recording head 105 is vertically installedon a bottom surface of the carriage 103 so as to lie on a rear side (onthe side of a timing belt 101) of the apparatus. Among the verticalwalls forming the holder 104, a vertical wall 108 which is close andopposite to the ink supply needles 106 and 107 has levers 111 and 112attached to an upper end thereof and which can be rotationally moved byshafts 109 and 110. A wall 113 located at a free end side of the levers111 and 112 has a vertical portion 113 a in a bottom side part and aninclined surface portion 113 b in an upper area, the inclined surfaceportion extending upward in a fashion fanning out.

The levers 111 and 112 have projections 114 and 115 formed to extendfrom the neighborhoods of the shafts 109 and 110 substantiallyperpendicularly to the body of the levers 111 and 112, the projectionsengaging with raised portions 145 and 156 located at upper ends of inkcartridges 140 and 150. The levers 111 and 112 also have hook sections118 and 119 that elastically engage with suspension portions 116 and 117formed on the inclined surface portion 113 b of the holder 104.

The levers 111 and 112 have elastic members 120 and 121, respectively,provided on a rear surface thereof (opposite to a cover 143 of the inkcartridge 140) as shown in FIGS. 20 and 21. The elastic members 120 and121 elastically press at least areas of the ink cartridges 140 and 150,respectively, which are opposite to ink supply ports 144 and 154 whenthe ink cartridges 140 and 150 are set in regular positions.

Further, a vertical wall 108 located closer to the ink supply needles106 and 107 has windows 122 and 123 with an open top portion. Verticalwalls 122 a and 123 a and bottom surfaces 122 b and 123 b forming thewindows 122 and 123, respectively, have continuous grooves 122 c and 123c, respectively, formed therein. Contact mechanisms 124 and 125 areinserted and fixed in the grooves 122 c and 123 c, respectively.

The recording head 105 is fixed to the bottom surface of the holder 104via a horizontal portion 133 of a generally L-shaped base 132. Avertical wall 134 of the base 132 has windows 135 and 136 in areasthereof which are opposite to the contact mechanisms 124 and 125,respectively, with a circuit substrate 130 held in front of the verticalwall 134.

The circuit substrate 130 is connected to the apparatus main bodycontrolling section 2 via a flexible cable 137 as shown in FIG. 16. Thecircuit substrate 130 has a gate array IC mounted thereon andconstituting the memory access controlling section 3.

FIG. 18 is a perspective view of the ink cartridge. FIG. 18(a) shows theblack ink cartridge 140, and FIG. 18(b) shows the color ink cartridge150. The ink cartridges 140 and 150 comprise generally rectangularparallelopiped containers 141 and 151 accommodating a porous body (notshown) with ink impregnated therewith, and the covers 143 and 153sealing top surfaces of the cartridges.

The containers 141 and 151 have the ink supply ports 144 and 145 formedin bottom surfaces thereof and at positions set opposite to the inksupply needles 106 and 107 when the containers are installed in inkcartridge housing sections 140 a and 104 a of the holder 104 shown inFIG. 16. Further, vertical walls 145 and 155 located on the side of theink supply ports 144 and 145 have the raised portions 146 and 145integrally formed at upper ends thereof and engaging with theprojections 114 and 115 of the levers 111 and 112.

The raised portion 146 of the black ink cartridge 140 is formed toextend continuously from one end to the other end. A triangular rib 147is formed between a bottom surface of the raised portion 146 and thevertical wall 145. The raised portion 156 of the color ink cartridge 150is formed individually on opposite sides of the vertical wall 155. Atriangular rib 157 is formed between a bottom surface of the raisedportion 156 and the vertical wall 155. Reference numeral 159 denotes amis-insertion preventing recess portion.

The vertical walls 145 and 155 have recess portions 148 and 158,respectively, located at the axial center of the ink cartridges 140 and150, respectively. Non-volatile memory circuit boards 131 and 131 areinstalled in the recess portions 148 and 158.

FIG. 19 is a view useful in explaining the structure of the non-volatilememory circuit board. FIG. 19(a) is a perspective view showing thefront-side structure of the non-volatile memory circuit board 131. FIG.19(b) is a perspective view showing the rear-side structure of thenon-volatile memory circuit board 131. FIG. 19(c) is a view useful inexplaining the size of electrodes. FIG. 19(d) is a top view showing howelectrodes and contacts contact with one another. FIG. 19(e) is a sideview showing how the electrodes and the contacts contact with oneanother.

As shown in FIG. 19(a), the non-volatile memory circuit board 131 has aplurality of electrodes 160 (160-1 and 160-2) disposed on its surface intwo rows in an ink cartridge inserting direction (vertical direction ofthe figure) and opposite to contact forming members 129 a and 129 b ofthe contact mechanism 124.

As shown in FIG. 19(b), the non-volatile memory circuit board 131 has anIC chip 161 of the non-volatile memories 4 and 5 mounted on its rearsurface. Terminals (not shown) of the IC chip 161 are electricallyconnected to the contacts 160 via a wiring pattern, through-holes, andthe like (not shown). The IC chip 161 of the non-volatile memories 4 and5 mounted on the non-volatile memory circuit board 131 may be protectedby coating it with an ink-resistant material.

As shown in FIG. 19(c), the smaller electrode 160-1 has a height H1 of1.8 mm and a width W1 of 1 mm. The larger electrode 160-2 has a heightH1 of 1.8 mm and a width W1 of 3 mm. The heights of the electrodes 160are set so as to reliably contact with the contact forming members 129 aand 129 b even if the ink cartridge 140 or 150 installed in the holder104 floats.

When the ink cartridges 140 and 150 are installed in the holder 104, theupper contact forming member 129 a of the contact mechanism 124 contactswith the upper electrode 160-1, while the lower contact forming member129 b of the contact mechanism 124 contacts with the lower electrodes160-1 and 160-2, as shown in FIGS. 19(d) and 19(e).

As shown in FIG. 19(d), the lower larger electrode 160-2 contacts withthe two contact forming members 129 a and 129 b. Whether or not the inkcartridge is installed is determined by detecting whether or not thesetwo contact forming members 129 a and 129 b are electrically connectedtogether.

Reference numeral 160T in FIG. 19 denotes an electrode used for checkingduring a manufacturing process or the like.

The non-volatile memory circuit board 131 has at least one through-hole131 a or a recess portion (notch) 131 b formed therein.

As shown in FIG. 18, the vertical walls 145 and 155 of the inkcartridges 140 and 150 have projections 145 a, 145 b, 155 a, and 155 bformed thereon and cooperating with the through-hole 131 a or the recessportion (notch) 131 b in the non-volatile memory circuit board 131 forpositioning. Furthermore, the vertical walls 145 and 155 have raisedportions 145 c, 145 d, 155 c, and 155 d such as ribs or claws whichelastically contact with a side surface of the non-volatile memorycircuit board 131.

Thus, when the non-volatile memory circuit board 131 is pressed againstthe vertical walls 145 and 155 of the ink cartridges 140 and 150, thenon-volatile memory circuit 131 can be positioned by the positioningprojections 145 a, 145 b, 155 a, and 155 b and engaged with the raisedportions 145 c, 145 d, 155 c, and 155 d for installation.

FIGS. 20 and 21 are views useful in explaining how the ink cartridge isinstalled. FIGS. 20 and 21 show a process of installing the black inkcartridge 140. As shown in FIG. 20, when the ink cartridge 140 isinserted into the holder 104 with the lever 111 opened to asubstantially vertical position, the raised portion 146 provided at oneend of the ink cartridge 140 is received by the projection 114 of thelever 111, and the other end of the ink cartridge 140 is supported andheld by the inclined surface portion 113 b of the holder 104.

In these conditions, when the lever 111 is closed, as shown in FIG. 21,the projection 114 is rotationally moved downward to cause the inkcartridge 140 to lower while substantially maintaining its positionestablished during an initial period of insertion, so that the inksupply port 144 comes into contact with a tip of the ink supply needle106.

When the lever 111 is further rotationally moved, the ink cartridge 140is pressed via the elastic member 120. The ink supply port 144 isthereby pushed over the ink supply needle 106. Then, when the lever 111is fully pushed in, it is fixed to the suspension portion 116 shown inFIG. 17 in such a manner that the ink cartridge 140 is alwayselastically pressed toward the ink supply needle 106 via the elasticmember 120.

The ink cartridge 140 is thereby elastically pressed at a constantpressure with the ink supply port 144 engaged with the ink supply needle106. Thus, the ink supply port 144 can remain stably and air-tightlyengaged with the ink supply needle 106 irrespective of impact orvibration associated with vibration during printing or movement of therecording apparatus.

FIG. 22 is a view useful in explaining how the non-volatile memorysubstrate and the contact forming member of the contact mechanismcontact with each other. FIG. 22(a) shows a state present before the inksupply port 144 in the ink cartridge 140 comes into contact with the inksupply needle 106 of the holder 104. FIG. 22(b) shows that the inksupply port 144 comes into contact with the ink supply needle 106. FIG.22(c) shows that the ink supply needle 106 is fully inserted into theink supply port 144 (the ink cartridge 140 is completely installed).

As shown in FIG. 22(c), when the ink cartridge 140 is completelyinstalled, the terminals (not shown) provided on the non-volatile memorycircuit substrate 131 contact with the contact forming members 129 a and129 b provided in the contact mechanism 124. Contact sections 128 a and128 b provided at the other end of the contact forming members 129 a and129 b, respectively, are in contact with the terminals (not shown)provided on the circuit board 130 with the memory access controllingsection 3 mounted thereon. The terminals provided on the non-volatilememory circuit 131 are thereby electrically connected via the contactforming members 129 a and 129 b to the corresponding terminals of thecircuit board 130 with the memory access controlling section 3 (notshown) mounted thereon.

In this embodiment, the ink jet printer apparatus is illustrated as therecording apparatus, but the recording apparatus according to thepresent invention is applicable to a laser printer apparatus using tonercartridges. Further, the recording apparatus according to the presentinvention is applicable not only to various printer apparatuses but alsoto facsimile terminal equipment or various terminal apparatusescomprising a cartridge-replaced recording mechanism. Furthermore, inthis embodiment, the configuration with the two non-volatile memories isshown, but only one non-volatile memory may be used. Moreover, thememory access controlling section may control writes to and readoutsfrom three or more non-volatile memories.

INDUSTRIAL APPLICABILITY

As described above, the recording apparatus according to the presentinvention is configured to execute writes to and readouts from thenon-volatile memory via the memory access controlling section, therebyreducing the amount of processing to be executed by the apparatus mainbody controlling section to access the non-volatile memory.

When the serial-data communicating section is provided to seriallycommunicate data between the apparatus main body controlling section andthe memory access controlling section, thus making it possible to reducethe number of signal lines required between the apparatus main bodycontrolling section and the memory access controlling section.

Further, the random access memory is provided, in which data read outfrom the non-volatile memory are all stored so that the stored data readout in response to a data readout request from the apparatus main bodycontrolling section, thus enabling a fast response to the data readoutrequest.

Furthermore, the apparatus main body controlling section can generate adata write request to renew data in the random access memory and thencause the data renewed in response to the data write request to bewritten to the non-volatile memory. Thus, even with a plurality of itemsto be renewed, the plurality of data can be written to the non-volatilememory with a single write operation.

Moreover, in the semiconductor device according to the presentinvention, the memory access controlling section is formed on thesemiconductor substrate to constitute an integrated circuit, therebycontributing to reducing the size of the recording apparatus.

Further, in the recording head apparatus according to the presentinvention, the memory access controlling section is thus provided in thecarriage comprising the section for housing the recording materialaccommodating cartridge, thereby facilitating the provision of thememory access controlling section.

1. A recording apparatus characterized by having a memory accesscontrolling section between an apparatus main body controlling sectionprovided in a recording apparatus main body and a non-volatile memoryprovided in a recording material accommodating cartridge, in order tocontrol writes to and readouts from said non-volatile memory based oncommands supplied by said apparatus main body controlling section, saidmemory access controlling section adapted to receive a mode set commandfrom the apparatus main body controlling section and operable to storean operation mode embodied in the mode set command in a mode register,said memory access controlling section having a random access memory fortemporarily storing data read out from said non-volatile memory, suchthat when said memory access controlling section receives a memoryaccess controlling operation mode command from said apparatus main bodycontrolling section, said apparatus main body controlling section causesdata stored in said non-volatile memory to be transferred to said randomaccess memory, causes various processes to be executed by referencingthe data stored in said random access memory to update the data storedin said random access memory, and then causes the data stored in saidrandom access memory to be transferred to said non-volatile memory. 2.The recording apparatus according to claim 1, characterized in that saidmemory access controlling section comprises a serial data communicatingsection for executing serial data communication with said apparatus mainbody controlling section, a command executing section for interpretingand executing a command supplied by said apparatus main body controllingsection via the serial data communicating section, and a non-volatilememory write and readout controlling section for executing writes to andreadouts from said non-volatile memory.
 3. The recording apparatus ofclaim 1 wherein the non-volatile memory is embodied in a black inkcartridge.
 4. The recording apparatus of claim 1 further comprises asecond non-volatile memory embodied in a color ink cartridge.
 5. Therecording apparatus of claim 4 wherein the memory access controllingsection further comprises a second random access memory for temporarilystoring data read out from said second non-volatile memory.
 6. Therecording apparatus of claim 1 wherein the memory access controllingsection further comprises a non-volatile memory write and readoutcontrolling section interposed between the random access memory and thenon-volatile memory, the non-volatile memory write and readoutcontrolling section operable to read information stored in thenon-volatile memory and store said information in the random accessmemory.
 7. The recording apparatus of claim 6 wherein the memory accesscontrolling section further comprises a plurality of control registersaccessible to the non-volatile memory write and readout controllingsection, each of the control registers assigned an address correspondingto a permission setting for the non-volatile memory.
 8. The recordingapparatus of claim 6 wherein the memory access controlling sectionfurther comprises an effective-bit-length data table accessible to thenon-volatile memory write and readout controlling section, where theeffective-bit-length data table stores correlation data betweeninformation residing in the non-volatile memory and a number of databits associated with said information.
 9. The recording apparatus ofclaim 8 wherein the non-volatile memory write and readout controllingsection partitions the information read from the non-volatile memory byusing the effective-bit-length data table, such that data having lessthan eight bits is supplemented with zeros to form 8-bit data and datahaving more than eight bits is modified to form two byte data.
 10. Therecording apparatus of claim 1 wherein the non-volatile memory write andreadout controlling section stores the modified data as composed sets of8 bits at predetermined addresses in random access memory.
 11. Asemiconductor device characterized by having a memory access controllingsection formed on a semiconductor substrate, for controlling writes toand readouts from a non-volatile memory based on commands supplied by anapparatus main body controlling section, said memory access controllingsection adapted to receive a mode set command from the apparatus mainbody controlling section and operable to store an operation modeembodied in the mode set command in a mode register, said memory accesscontrolling section having a random access memory for temporarilystoring data read out from said non-volatile memory, said apparatus mainbody controlling section causes data stored in said non-volatile memoryto be transferred to said random access memory, causes various processesto be executed by referencing the data stored in said random accessmemory to update the data stored in said random access memory, and thencauses the data stored in said random access memory to be transferred tosaid non-volatile memory when said memory access controlling sectionreceives a memory access controlling operation mode command from theapparatus main body controlling section.
 12. A recording head apparatuscharacterized by having a section for housing a recording materialaccommodating cartridge including a non-volatile memory has a memoryaccess controlling section for controlling data transmissions andreceptions between a control section of a recording apparatus main bodyand said non-volatile memory based on commands supplied by said controlsection of said recording apparatus main body, said memory accesscontrolling section adapted to receive a mode set command from theapparatus main body controlling section and operable to store anoperation mode embodied in the mode set command in a mode register, saidmemory access controlling section having a random access memory fortemporarily storing data read out from said non-volatile memory, saidapparatus main body controlling section causes data stored in saidnon-volatile memory to be transferred to said random access memory,causes various processes to be executed by referencing the data storedin said random access memory to update the data stored in said randomaccess memory, and then causes the data stored in said random accessmemory to be transferred to said non-volatile memory when said memoryaccess controlling section receives a memory access controllingoperation mode command from said apparatus main body controllingsection.